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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
64-KByte Block-Erase for SST25WF020 and SST25WF040
The Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area is ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain active low for the duration of any command
sequence. The Block-Erase instruction is initiated by executing an 8-bit command, D8H, followed by
address bits [A 23 -A 0 ]. Address bits [A MS -A 16 ] (A MS = Most Significant Address) are used to determine
block address (BA X ), remaining address bits can be V IL or V IH. CE# must be driven high before the instruc-
tion is executed. Poll the Busy bit in the software status register or wait T BE for the completion of the inter-
nal self-timed Block-Erase. See Figure 15 for the Block-Erase sequences.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31
SCK
MODE 0
SI
D8
ADDR
ADDR
ADDR
SO
MSB
MSB
HIGH IMPEDANCE
1328 F15.0
Figure 15: 64-KByte Block-Erase Sequence
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction is ignored if
any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must
be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The
Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high
before the instruction is executed. The user may poll the Busy bit in the software status register or wait T CE
for the completion of the internal self-timed Chip-Erase cycle. See Figure 16 for the Chip-Erase
sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7
SCK
SI
SO
MODE 0
60 or C7
MSB
HIGH IMPEDANCE
1328 F16.0
Figure 16: Chip-Erase Sequence
?2011 Silicon Storage Technology, Inc.
19
DS25016A
06/11
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